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s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 1 174-3.0 SED1560/1/2 technical manual (preliminary) s-mos systems, inc. october, 1996 version 3.0 (preliminary)
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s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 3 174-3.0 table of contents SED1560 series table of contents 1.0 overview ................................................................................................................................................... 5 1.1 description .................................................................................................................................... 7 1.2 features ........................................................................................................................................ 7 1.3 system block diagrams ................................................................................................................ 7 1.4 block diagram ............................................................................................................................... 9 2.0 pin description ....................................................................................................................................... 11 2.1 power supply .............................................................................................................................. 13 2.2 lcd driver power supplies ......................................................................................................... 13 2.3 microprocessor interface ............................................................................................................. 14 2.4 oscillator and display timing control ......................................................................................... 15 2.5 lcd driver outputs ..................................................................................................................... 16 3.0 electrical characteristics ...................................................................................................................... 17 3.1 absolute maximum ratings ......................................................................................................... 19 3.2 dc characteristics ...................................................................................................................... 20 3.3 ac characteristics........................................................................................................................ 24 3.3.1 reset ............................................................................................................................ 24 3.4 display control timing ................................................................................................................ 25 3.5 system buses: read/write characteristics i (80-series mpu) ................................................... 27 3.6 system buses: read/write characteristics ii (68-series mpu) .................................................. 28 3.7 serial interface ............................................................................................................................ 30 4.0 functional description .......................................................................................................................... 33 4.1 microprocessor interface ............................................................................................................. 35 4.1.1 parallel/serial interface ................................................................................................ 35 4.1.2 parallel interface ........................................................................................................... 35 4.1.3 serial interface ............................................................................................................. 35 4.1.4 chip select inputs ........................................................................................................ 36 4.2 data transfer .............................................................................................................................. 36 4.3 status flag .................................................................................................................................. 38 4.4 display data ram ....................................................................................................................... 38 4.5 column address counter ............................................................................................................ 38 4.6 page address register ............................................................................................................... 38 4.7 initial display line register ......................................................................................................... 40 4.8 output selection circuit............................................................................................................... 40 4.9 SED1560 output status .............................................................................................................. 42 4.10 sed1561 output status ............................................................................................................ 42 4.11 sed1562 output status ............................................................................................................ 43 4.12 display timers ........................................................................................................................... 43 4.12.1 line counter and display data latch timing ............................................................. 43 4.12.2 fr and sync ............................................................................................................. 43 4.12.3 common timing signals ............................................................................................ 43 4.13 two-frame ac driver waveform (sed1561, 1/32 duty) ............................................................ 44 4.14 n line inverse driver waveform (n-5, line inverse register 4) .................................................. 45 4.15 display data latch .................................................................................................................... 46
4 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 SED1560 series table of contents 4.16 lcd driver ................................................................................................................................. 46 4.17 display data latch circuit ......................................................................................................... 46 4.18 lcd driver circuit ..................................................................................................................... 46 4.19 oscillator circuit ........................................................................................................................ 46 4.20 fr control circuit ...................................................................................................................... 46 4.21 power supply circuit ................................................................................................................. 48 4.22 tripler boosting circuit .............................................................................................................. 48 4.23 voltage regulation circuit (software contrast adjustment function is not used) ................... 49 4.24 voltage regulation circuit using software contrast adjustment control function .................. 50 4.25 precautions on using the SED1560 series software contrast adjustment control function .. 51 4.26 liquid crystal voltage generating circuit ................................................................................. 54 4.27 reset ......................................................................................................................................... 56 5.0 commands .............................................................................................................................................. 57 5.1 command summary .................................................................................................................. 59 5.2 command definitions ................................................................................................................. 60 5.3 software contrast control register............................................................................................. 67 5.4 microprocessor interface ............................................................................................................. 69 5.5 lcd panel interface examples ................................................................................................... 70 5.6 special common driver configurations ...................................................................................... 72 6.0 packaging ............................................................................................................................................... 73 6.1 pad layout .................................................................................................................................. 75 6.2 SED1560/1/2 tab pin layout ..................................................................................................... 77 6.3 tcp dimensions (2-sided) .......................................................................................................... 78 6.4 tcp dimensions (4-sided) .......................................................................................................... 79 6.5 tcp dimensions (d1561toc) .................................................................................................... 80 6.6 pad profile ................................................................................................................................... 81 6.7 bga package dimensions .......................................................................................................... 82 6.8 bga pin assignment ................................................................................................................... 83 6.9 SED1560tqa ol dimensions .................................................................................................... 84
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 5 174-3.0 1.0 overview
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s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 7 174-3.0 1.0 overview 1.0 C 1.3 1.1 description the SED1560 series are intelligent cmos lcd driver- controllers with the ability to drive alphanumeric and graphic displays. the SED1560 series communicates with a high-speed microprocessor, such as the intel 80xx family or the motorola 68xx family, through either a serial or an 8-bit parallel interface. it stores the data sent from the microprocessor in the built-in display data ram (166 65 bits) and generates an lcd drive signal. these devices incorporate an internal dc/dc converter to generate the negative voltage needed for lcd contrast. the controllers feature software contrast adjustment by command setting. the three different versions of the SED1560 series support the following duty ratios and display sizes: model duty ratio seg com SED1560 1/65, 1/64, 1/49, 1/48 102 65 sed1561 1/33, 1/32, 1/25, 1/24 134 33 sed1562 1/17, 1/16 150 17 1.2 features ? low-power operation: 8 m a @ 1 khz, 6v lcd ? 350 m a current consumption during cpu access @ 200 khz ? direct interface to both 80xx and 68xx, 5 mhz, zero wait-state ? on-chip display data ram (166 65 bits) ? on-chip dc/dc converter for lcd voltage ? on-chip voltage regulator and low-power volt- age follower ? C.17% / c temperature gradient ? on-chip oscillator with external resistor ? 32 levels of contrast adjustment by software ? supports master/slave operation ? selectable output configuration ? 2.4v to 6.0v supply voltage ? 3.5v to 16v lcd voltage ? package: tab 2 side t0b tab 4 side tqa al pad d*a au bump d*b bga 225 pad b0a 1.3 system block diagrams 20 char 8 lines SED1560 cpu 80xx 68xx res cs d0 ~ d7
8 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 1.3 1.0 overview 1.3 system block diagrams (cont.) 26 char 4 lines sed1561 cpu 80xx 68xx res cs d0 ~ d7 seg0~seg133 com0~com32 30 char 2 lines sed1562 cpu 80xx 68xx res cs d0 ~ d7
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 9 174-3.0 v ss v dd v1 v2 v3 v4 v5 common and segment drivers segment driver common and segment drivers commons only frame control shift register shift register 166-bit display data latch 166 x 65-bit display data ram 166-bit column address decoder 8-bit column address counter 8-bit column address register line address decoder i/o buffer line counter display initial line register output status select page address register lcd supply voltage generator display timing generator bus holder status flag oscillator command decoder mpu interface i/o buffer v dd v1 v2 v3 v4 v5 fr sync cl clo dyo m/s osc1 osc2 cs1 cs2 a0 rd wr c86 si scl p/s res d7 d6 d5 d4 d3 d2 d1 d0 com1 o165 o102 o101 o32 o31 o00 to to to cap1+ cap1 cap2+ cap2 v r t1, t2 1.0 overview 1.4 1.4 block diagram
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s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 11 174-3.0 2.0 pin description
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s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 13 174-3.0 2.0 pin description 2.1 C 2.2 number of pins i/o name description 2 supply v dd common to mpu power supply pin v cc 2 supply v ss ground 11 v1 to v5 lcd driver supply voltages. the voltage determined by the lcd cell is impedance-converted by a resistive divider or an operational amplifier for application. voltage levels are based on v dd . the voltages must satisfy the following relationship: v dd 3 v1 3 v2 3 v3 3 v4 3 v5 master mode select: bias voltages are generated on-chip. 2.1 power supply SED1560 sed1561 sed1562 v1 1/9 v5 1/7 v5 1/5 v5 v2 2/9 v5 2/7 v5 2/5 v5 v3 7/9 v5 5/7 v5 3/5 v5 v4 8/9 v5 6/7 v5 4/5 v5 boosting voltage t1 t2 circuit regulation v/f circuit circuit l l valid valid valid l h valid valid valid* h l invalid valid valid h h invalid invalid valid * v/f circuit current capacity enhancement 2.2 lcd driver power supplies number of pins i/o name description 1 o cap1+ dc/dc voltage converter capacitor 1 positive connection 1 o cap1C dc/dc voltage converter capacitor 1 negative connection 1 o cap2+ dc/dc voltage converter capacitor 2 positive connection 1 o cap2C dc/dc voltage converter capacitor 2 negative connection 1ov out dc/dc voltage converter output 1iv r voltage adjustment pin. applies voltage between v dd and v5 using a resistive divider. 2 i t1, t2 liquid crystal power control terminals supply lcd voltage
14 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 2.3 microprocessor interface number of pins i/o name description 8 i/o d0 to d7 data is transferred between the controller and mpu via these pins 1 i a0 control/display data flag input. this is connected to the lsb of the microprocessor address bus. ? when low, the data on d0 to d7 is command data ? when high, the data on d0 to d7 is display data 1 i res reset input. setting this pin low initializes the sed156x. 2 i cs1, chip select inputs. data input/output is enabled when cs1 is low cs2 and cs2 is high. 1 i rd read enable input. see note 1. 1 i wr write enable input. see note 2. 1 i c86 microprocessor interface select input. ? low when interfacing to 8080-series ? high when interfacing to 6800-series 1 i si serial data input 1 i scl serial clock input. data is read on the rising edge of scl and converted to 8-bit parallel data. 1 i p/s parallel/serial data input select in serial mode, data cannot be read from the ram, and d0 to d7, hz, rd and wr must be high or low. in parallel mode, si and scl must be high or low. notes: 1. when interfacing to 8080-series microprocessors, rd is active-low. when interfacing to 6800-series microprocessors, they are active-high. 2. when interfacing to 8080-series microprocessors, wr is active-low. when interfacing to 6800-series microprocessors, read mode is selected when wr is high, and write mode is selected when wr is low. 2.3 2.0 pin description operating chip data/ data read/ serial p/s mode select com- i/o write clock mand high parallel cs1, cs2 a0 d0 to rd, wr d7 low serial cs1, cs2 a0 si write only scl
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 15 174-3.0 2.0 pin description 2.4 2.4 oscillator and display timing control number of pins i/o name description 2 i osc1 using internal oscillator when m/s = h, connect resistor r f to the osc1 and osc2 pins. the osc2 pin is used for output of the oscillator amplifier. 2 i/o osc2 when m/s = l: the osc2 pin is used for input of oscillation signal. the osc1 pin should be left open. fix the c l pin to the v ss level when using the internal oscillator circuit as the display clock. 1ic l display clock input. the line counter increments on the rising edge of c l , and the display pattern is output on the falling edge. when using the external display clock, osc1 = h, osc2 = l, and reset this lsi by res pin. 1oc lo display clock output. when using the internal oscillator, the clock signal is output on this pin. connect c lo to yscl on the common driver. 1 i m/s master/slave select input. master produces signals for display, and slave receives them. this is for display synchronization. device m/s operating internal power fr sync osc1 osc2 dyo mode oscillator supply 156x low slave off off i i open i o high master on on o o i o o note: i = input mode o = output mode 1 i/o fr lcd ac drive signal input/output. output is selected when m/s is high, and input is selected when m/s is low. 1 i/o sync display sync input/output. output is selected when m/s is high, and input is selected when m/s is low. 1 o dyo start-up output for common driver. connect to dio of the common driver, such as the sed1630. * sed1630 has a dio input.
16 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 scan data fr lcd on voltage low low v4 high v1 high low v dd high v5 2.5 2.0 pin description 2.5 lcd driver outputs number of pins i/o name description 166 o o0 to lcd driver outputs. o0 to o31 and o102 to o165 are selectable o165 segment or common outputs, determined by a selection command. o32 to o101 are segment outputs only. for segment outputs, the on voltage level is given as shown in the following table: ram data fr lcd on voltage normal display inverse display low low v3 v5 high v2 v dd high low v5 v3 high v dd v2 for common outputs, the on voltage is given as shown in the follow- ing table: 1 o com1 lcd driver common output. common outputs when the duty + 1 command is executed are as follows: device duty + 1 on duty + 1 off SED1560 com64, com48 v1 or v4 sed1561 com32, com24 v1 or v4 sed1562 com16 v1 or v4 common output special for the indicator.
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 17 174-3.0 3.0 electrical characteristics
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s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 19 174-3.0 3.0 electrical characteristics 3.1 3.1 absolute maximum ratings parameter symbol rating unit C7.0 to 0.03 supply voltage range v ss C6.0 to 0.3 v (when triple voltage conversion) driver supply voltage range (1) v5 C18.0 to 0.3 v driver supply voltage range (2) v1, v2, v3, v4 v5 to 0.3 v input voltage range v in v ss C0.3 to 0.3 v output voltage range v0 v ss C0.3 to 0.3 v operating temperature range t opr C30 to 85 c storage temperature range (tcp) t str C55 to 125 c notes: 1. the voltages shown are based on v dd = 0v. 2. always keep the condition v dd 3 v1 3 v2 3 v3 3 v4 3 v5 for voltages v1, v2, v3 and v4. 3. if devices are used over the absolute maximum rating, the lsis may be destroyed permanently. it is desirable to use them under the electrical characteristic conditions for general operation. otherwise, a malfunction of the lsi may be caused and lsi reliability may be affected. 4. for operating temperatures below C30 c, please consult an s-mos engineer.
20 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 3.2 3.0 electrical characteristics parameter symbol condition min typ max unit applicable pin recommended C5.5 C5.0 C4.5 v ss operation operational C6.0 C2.4 v ss *1 operational v5 C16.0 C3.5 v v5 *2 operational v1, v2 0.4 v5 v dd v v1, v2 operational v3, v4 v5 0.6 v5 v v3, v4 v ihc1 0.3 v ss v dd v*3 high-level input voltage v ihc2 0.15 v ss v dd v*4 v ihc1 v ss = C2.7v 0.2 v ss v dd v*3 v ihc2 v ss = C2.7v 0.15 v ss v dd v*4 v ilc1 v ss 0.7 v ss v*3 low-level input voltage v ilc2 v ss 0.85 v ss v*4 v ilc1 v ss = C2.7v v ss 0.8 v ss v*3 v ilc2 v ss = C2.7v v ss 0.85 v ss v*4 v ohc1 i oh = C1 ma 0.2 v ss v dd v *5 high-level output voltage v ohc2 i oh = C120 m a 0.2 v ss v dd osc2 v ohc1 v ss = C2.7v i oh = C0.5 ma 0.2 v ss v dd v *5 v ohc2 v ss = C2.7v i oh = C50 m a 0.2 v ss v dd osc2 v olc1 i ol = 1 ma v ss 0.8 v ss v *5 low-level output voltage v olc2 i ol = 120 m av ss 0.8 v ss osc2 v olc1 v ss = C2.7v i ol = 0.5 ma v ss 0.8 v ss v *5 v olc2 v ss = C2.7v i ol = 50 m av ss 0.8 v ss osc2 input leakage current i li v in = v dd or v ss C1.0 1.0 m a*6 output leakage current i lo C3.0 3.0 m a*7 lcd driver on resistance r on t a = 25 c v5 = C14.0v 2.0 3.0 k w o0 ~ o166 v5 = C8.0v 3.0 4.5 *8 static power consumption i ssq 0.00 5.0 m av ss i 5q v5 = C18.0v 0.01 15.0 m av5 input terminal capacity c in t a = 25 c f = 1 mhz 5.0 8.0 pf *3 *4 oscillator frequency f osc r f = 1 m w v ss = C5v 15 18 22 khz *9 2% v ss = C2.7v 11 16 21 reset time t r 1.0 m s *10 reset l pulse width t rw 10 m s *11 (continued) power voltage (1) v v ss operating voltage (2) v dd = 0v, v ss = C5 10%, t a = C30 to +85 c unless otherwise noted. 3.2 dc characteristics
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 21 174-3.0 typical current consumption characteristics ? dynamic current consumption (i), if an external clock and an external power supply are used. conditions: the built-in power supply is off but the external one is used. SED1560 ......... v5 = C12.5v sed1561 ......... v5 = C8.0v sed1562 ......... v5 = C6.0v external clock: SED1560 ......... f cl = 4 khz sed1561 ......... f cl = 2 khz sed1562 ......... f cl = 1 khz remarks: *14 test conditions, unless otherwise specified: v dd = 0v, v ss = C5v 10%, t a = C30 to 85 c parameter symbol condition min typ max unit remarks SED1560 v5 = C12.5v; 3 times amplified 169 340 m a sed1561 v5 = C8.0v; 3 times amplified 124 250 m a sed1562 v5 = C6.0v; 2 times amplified 53 110 m a v ss = C2.7v; 3 times amplified 66 130 m a v5 = C6.0v 3.0 electrical characteristics 3.2 parameter symbol condition min typ max unit applicable pin input voltage v ss C6.0 C2.4 v *12 amplified output voltage v out C18.0 v v out voltage regulator v out C18.0 C6.0 v v out circuit operation voltage v5 1 supplied to SED1560 C16.0 C6.0 v v5 2 supplied to sed1561 C16.0 C5.0 v *13 v5 3 supplied to sed1562 C16.0 C4.5 v reference voltage v reg t a = 25 c C2.35 C2.5 C2.65 v if amplified 3 times voltage follower operation voltage built-in power circuit *16 i dd (1) when dynamic current consumption (i) is displayed; the built-in power supply is on and t1 = t2 = low. (continued) v dd = 0v, v ss = C5 10%, t a = C30 to +85 c unless otherwise noted. notes: * see notes on page 22. 40 30 20 10 0 ? ? ? ? ? ? ? i dd (1) (i ss +i5) v ss (v) (?) SED1560 sed1561 sed1562
22 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 ? dynamic current consumption (i), if the built-in oscillator and the external power supply are used. conditions: the built-in power supply is off but the external one is used. SED1560 ......... v5 = C12.5v sed1561 ......... v5 = C8.0v sed1562 ......... v5 = C6.0v internal oscillation: SED1560 ......... rf = 1 m w sed1561 ......... rf = 1 m w sed1562 ......... rf = 1 m w remarks: *15 ? dynamic current consumption (i), if the built-in power supply is used. conditions: the built-in power supply is on and t1 = t2 = low. SED1560 ......... v5 = C12.5v; 3 times amplified sed1561 ......... v5 = C8.0v; 3 times amplified sed1562 ......... v5 = C6.0v; 2 times amplified internal oscillation: SED1560 ......... r f = 1 m w sed1561 ......... r f = 1 m w sed1562 ......... r f = 1 m w remarks: *16 200 150 100 50 0 ? ? ? ? ? ? ? i dd (1) (?) v ss (v) SED1560 sed1561 sed1562 notes: *1. a wide range of operating voltage is possible, but considerable voltage variation during mpu access is not guaranteed. *2. the operating voltage range of the v ss and v5 systems (see figure 3.3). the operating voltage range is applied if an external power supply is used. *3. pins a0, d0 to d7, rd (e),wr (r/w), cs1, cs2, fr, sync, m/s, c86, si, p/s, t1 and t2. *4. pins cl, scl, and res. *5. pins d0 to d7, fr, sync, cl0, and dy0 *6. pins a0, rd (e), wr (r/w), cs1, cs2, cl, m/s, res, c86, si, scl, p/s, t1, and t2. *7. applied if pins d0 to d7, fr, and sync are high impedance. *8. the resistance when the 0.1 -volt voltage is applied between the on output terminal and each power terminal (v1, v2, v3 or v4). it must be within the operating voltage (2). *9. the relationship between the oscillation frequency, frame and rf value (see figure 3.2). *10. tr (reset time) indicates the period between the time when the res signal rises and when the internal circuit has been reset. therefore, the sed156* is usually operable after tr time. *11. specifies the minimum pulse width of res signal. the low pulse greater than t rw must be entered for reset. *12. if the voltage is amplified three times by the built-in power circuit, the primary power v ss must be used within the input voltage range. *13. the v5 voltage can be adjusted within the voltage follower operat- ing range by the voltage regulator circuit. *14, 15, 16. indicates the current consumed by the separate ic. the current consumption due to the lcd panel capacity and wiring capacity is not included. the current consumption is shown if the checker is used, the display is turned on, the output status of case 6 is selected, and the SED1560 is set to 1/64 duty, the sed1561 is set to 1/32 duty, and the sed1562 is set to 1/64 duty. *14. applied if an external clock is used and if not accessed by the mpu. *15. applied if the built-in oscillation circuit is used and if not accessed by the mpu. *16. applied if the built-in oscillation circuit and the built-in power circuit are used (t1 = t2 = low) and if not accessed by the mpu. 3.2 3.0 electrical characteristics 80 60 40 20 0 ? ? ? ? ? ? ? i dd (1) (i ss +i5) v ss (v) (?) SED1560 sed1561 sed1562
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 23 174-3.0 the relationship between oscillator frequency f osc and lcd frame frequency f f is obtained from the following expression: table 3.1 device duty f f SED1560 1/64 f osc/256 1/48 f osc/192 sed1561 1/32 f osc/256 1/24 f osc/192 sed1562 1/16 f osc/256 (f f indicates not f f signal cycle but cycle of lcd ac.) figure 3.1 oscillator frequency vs. frame vs. r f [SED1560 series] 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 [khz] f osc rf [m? ta = 25? v ss = ?v 200 100 02 [hz] f f f cl [khz] 468 duty 1/64 SED1560 duty 1/48 duty 1/32 sed1561 duty 1/24 duty 1/16 sed1562 figure 3.2 external clock (f cl ) vs. frame frequency [SED1560 series] 3.0 electrical characteristics 3.2
24 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 3.2 C 3.3.1 3.0 electrical characteristics figure 3.3 operating voltage range for v ss and v5 figure 3.4 power consumption during cpu access cycle (i dd [2]) 10 1 0.1 0.01 0 [ma] i dd (2) 0.01 0.1 1 10 f cyc [mhz] 2.7v 5.0v ?0 ?5 ?0 ? 02 [v] v5 v ss [v] ? ? ? ?.4 ?.0 ?6 ?3 3.3 ac characteristics 3.3.1 reset table 3.5 reset parameter symbol condition rating unit min typ max t r is measured from the rising edge reset time t r of res. the sed156x resumes 1.0 m s normal operating mode after a reset. reset low-level t rw 1.0 m s pulsewidth
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 25 174-3.0 3.0 electrical characteristics 3.4 3.4 display control timing display control input timing v ss = C5.5 to C4.5v, t a = C30 to 85 c parameter symbol condition rating unit min typ max cl low-level pulsewidth t wlcl 35 m s cl high-level pulsewidth t whcl 35 m s cl rise time t r 30ns cl fall time t f 30ns fr delay time t dfr C1.0 1.0 m s sync delay time t dsnc C1.0 1.0 m s v ss = C4.5 to C2.7v, t a = C30 to 85 c parameter symbol condition rating unit min typ max cl low-level pulsewidth t wlcl 35 m s cl high-level pulsewidth t whcl 35 m s cl rise time t r 40ns cl fall time t f 40ns fr delay time t dfr C1.0 1.0 m s sync delay time t dsnc C1.0 1.0 m s 1. effective only when the sed156x is in the master mode. 2. the fr/sync delay time input timing is provided in the slave operation. the fr/sync delay time output timing is provided in the master operation. 3. each timing is based on 20% and 80% of v ss . figure 3.5 display control timing t wlcl t whcl t r t f t dfr t dsnc t dol t cdl t cdh t doh cl fr sync dyo clo
26 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 3.4 3.0 electrical characteristics display control output timing v ss = C5.5 to C4.5v, t a = C30 to 85 c parameter symbol condition rating unit min typ max fr delay time t dfr c l = 50 pf 60 150 ns sync delay time t dsnc c l = 100 pf 60 150 ns dyo low-level delay time t dol 70 160 ns dyo high-level delay time t doh 70 160 ns clo to dyo low-level t cdl sed156x operating in 40 100 ns delay time master mode only clo to dyo high-level t cdh sed156x operating in 40 100 ns delay time master mode only v ss = C4.5 to C2.7v, t a = C30 to 85 c parameter symbol condition rating unit min typ max fr delay time t dfr c l = 50 pf 120 240 ns sync delay time t dsnc c l = 100 pf 120 240 ns dyo low-level delay time t dol 140 250 ns dyo high-level delay time t doh 140 250 ns clo to dyo low-level t cdl sed156x operating in 100 200 ns delay time master mode only clo to dyo high-level t cdh sed156x operating in 100 200 ns delay time master mode only
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 27 174-3.0 3.0 electrical characteristics 3.5 3.5 system buses: read/write characteristics i (80-series mpu) t cclr t cclw t cchr t cchw a0 wr, rd, (cs) d0 to d7 (write) d0 to d7 (read) t ds8 t cyc8 t ah8 t dh8 t f t r t ch8 t acc8 t aw8 parameter signal symbol condition min max unit address hold time a0, cs t ah8 10 ns address setup time t aw8 10 ns system cycle time t cyc8 200 ns control l pulse width (wr) wr t cclw 22 ns control l pulse width (rd) rd t cclr 77 ns control h pulse width (wr) wr t cchw 172 ns control h pulse width (rd) rd t cchr 117 ns data setup time t ds8 20 ns data hold time t dh8 10 ns rd access time d0 ~ d7 t acc8 cl = 100pf 70 ns output disable time t ch8 10 50 ns input signal change time t r , t f 15ns v ss = C5.0 10%, t a = C30 to 85 c
28 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 parameter signal symbol condition min max unit address hold time a0, cs t ah8 25 ns address setup time t aw8 25 ns system cycle time t cyc8 450 ns control l pulse width (wr) wr t cclw 44 ns control l pulse width (rd) rd t cclr 194 ns control h pulse width (wr) wr t cchw 394 ns control h pulse width (rd) rd t cchr 244 ns data setup time t ds8 40 ns data hold time t dh8 20 ns rd access time d0 ~ d7 t acc8 cl = 100pf 140 ns output disable time t ch8 10 100 ns input signal change time t r , t f 15ns v ss = C2.7 to C4.5v, t a = C30 to 85 c notes: 1. when using the system cycle time in the high-speed mode, it is limited by t r + t f (t cyc8 C t cclw C t cchw ) or t r + t f (t cyc8 C t cclr C t cchr ) 2. all signal timings are limited based on 20% and 80% of v ss voltage. 3. read/write operation is performed while cs (cs1 and cs2) is active and the rd or wr signal is in the low level. if read/write operation is performed by the rd or wr signal while cs is active, it is determined by the rd or wr signal timing. if read/write operation is performed by cs while the rd or wr signal is in the low level, it is determined by the cs active timing. 3.5 C 3.6 3.0 electrical characteristics 3.6 system buses: read/write characteristics ii (68-series mpu) t aw6 t r t ewhw t ewhr t ewlw t ewlr t ah6 t ah6 t oh6 t acc6 t dh6 t ds6 t f t cyc6 e a0, rw d0 ~ d7 (write) d0 ~ d7 (read)
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 29 174-3.0 parameter signal symbol condition min max unit system cycle time t cyc6 200 ns address setup time (a0) t aw6 10 ns address hold time r/w t ah6 10 ns data setup time t ds6 20 ns data hold time d0 ~ d7 t dh6 10 ns output disable time t oh6 cl = 100pf 10 50 ns access time t acc6 70ns enable h pulse read e t ewhr 77 ns width write t ewhw 22 ns enable l pulse read e t ewlr 117 ns width write t ewlw 172 ns input signal change time t r , t f 15ns v ss = C5.0 10%, t a = C30 to 85 c parameter signal symbol condition min max unit system cycle time a0, cs t cyc6 450 ns address setup time (cs1, cs2) t aw6 25 ns address hold time r/w t ah6 25 ns data setup time t ds6 40 ns data hold time d0 ~ d7 t dh6 20 ns output disable time t oh6 cl = 100pf 20 100 ns access time t acc5 140 ns enable h pulse read e t ewhr 154 ns width write t ewhw 44 ns enable l pulse read e t ewlr 244 ns width write t ewlw 394 ns input signal change time t r , t f 15ns v ss = C2.7 to +4.5v, t a = C30 to 85 c notes: 1. when using the system cycle time in the high-speed mode, it is limited by t r + t f (t cyc6 C t ewlw C t ewhw ) or t r + t f (t cyc6 C t ewlr C t ewhr ) 2. all signal timings are limited based on 20% and 80% of v ss voltage. 3. read/write operation is performed while cs (cs1 and cs2) is active and the e signal is in the high level. if read/write operation is performed by the e signal while cs is active, it is determined by the e signal timing. if read/write operation is performed by cs while the e signal is in the high level, it is determined by the cs active timing. 3.0 electrical characteristics 3.6
30 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 3.7 3.0 electrical characteristics 3.7 serial interface t css t sas t sah t csh t sdh t shw t r t f t sds cs a0 scl si t slw t scyc
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 31 174-3.0 parameter signal symbol condition min max unit serial clock cycle t scyc 500 ns scl high pulse width scl t shw 150 ns scl low pulse width t slw 150 ns address setup time a0 t sas 120 ns address hold time t sah 200 ns data setup time si t sds 120 ns data hold time t sdh 50 ns cs-scl time cs t css 30 ns t csh 400 ns input signal change time t r , t f 50ns v ss = C5.0 10%, t a = C30 to 85 c parameter signal symbol condition min max unit serial clock cycle t scyc 1000 ns scl high pulse width scl t shw 300 ns scl low pulse width t slw 300 ns address setup time a0 t sas 250 ns address hold time t sah 400 ns data setup time si t sds 250 ns data hold time t sdh 100 ns cs-scl time cs t css 60 ns t csh 800 ns input signal change time t r , t f 50ns v ss = C2.7 to C4.5v, t a = C30 to 85 c note: *2. all signal timings are limited based on 20% and 80% of v ss voltage. 3.0 electrical characteristics 3.7
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s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 33 174-3.0 4.0 functional description
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s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 35 174-3.0 4.0 functional description 4.0 C 4.1.3 4.1 microprocessor interface 4.1.1 parallel/serial interface table 4.1 parallel/serial interface selection p/s input type cs1 cs2 a0 rd wr c86 si scl d0 to d7 high parallel cs1 cs2 a0 rd wr c86 d0 to d7 low serial cs1 cs2 a0 si scl (hi-z) = dont care parallel data can be transferred in either direction between the controlling microprocessor and the SED1560 series via an 8-bit i/o buffer (d0 to d7). serial data can be sent from the microprocessor to the SED1560 series through the serial data input (si), but not from the SED1560 series to the microprocessor. the parallel or serial interface is selected by setting p/s as shown in table 4.1. for the parallel interface, the type of microprocessor is selected by c86 as shown in table 4.2. table 4.2 microprocessor selection for parallel interface c86 mpu cs1 cs2 a0 rd wr d0 to d7 bus type high 6800-series cs1 cs2 a0 e r/w d0 to d7 low 8080-series cs1 cs2 a0 rd wr d0 to d7 4.1.2 parallel interface a0, wr (or r/w) and rd (or e) determine the type of parallel data transfer. see table 4.3. table 4.3 parallel data transfer com- 6800 8080 series mon series a0 r/w rd wr 1101 display data read out 1010 display data write 0101 status read 0010 write to internal register (command) description 4.1.3 serial interface the serial interface consists of an 8-bit shift register and a 3-bit counter. these are reset when cs1 is high and cs2 is low. when these states are reversed, serial data and clock pulses can be received from the micro- processor on si and scl respectively. serial data is read on the rising edge of scl and must be input at si in the sequence d7 to d0. on every eighth clock pulse, the data is transferred from the shift register and processed as 8-bit parallel data. input data is display data when a0 is high and com- mand data when a0 is low. a0 is read on the rising edge of every eighth clock signal. see figure 4.1.
36 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 4.1.3 C 4.2 4.0 functional description d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 10 9 8 7 6 5 4 3 2 1 cs1 cs2 si scl a0 figure 4.1 serial interface timing 4.1.4 chip select inputs data transfer between the microprocessor and the SED1560 series is enabled when cs1 is low and cs2 is high. if these pins are set to any other values, d0 to d7 are in high impedance state and will not accept data. likewise, when the microprocessor writes data to dis- play data ram, the data is first stored in the bus buffer before being written to ram at the next write cycle. when writing data from the microprocessor to ram, there is no delay since data is automatically trans- ferred from the bus buffer to the display data ram. if the data rate is required to slow down, the micropro- cessor can insert a nop instruction which has the same effect as executing a wait procedure. when a sequence of address sets is executed, a dummy read cycle must be inserted between each pair of address sets. this is necessary because the addressed data from the ram is delayed one cycle by the bus buffer, before it is sent to the microprocessor. a dummy read cycle is thus necessary after an address set and after a write cycle. 4.2 data transfer to match the timing of the display data ram and registers to that of the controlling microprocessor, the SED1560 series uses an internal data bus and bus buffer. when the microprocessor reads the contents of ram, the data for the initial read cycle is first stored in the bus buffer (dummy read cycle). on the next read cycle, the data is read from the bus buffer onto the microprocessor bus. at the same time, the next block of data is transferred from ram to the bus buffer.
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 37 174-3.0 4.0 functional description 4.2 mpu n n+1 n+2 n+3 n n+1 n+2 n+3 internal timing bus holder wr wr data figure 4.2 write timing mpu internal timing wr rd data n n n+1 n+2 n n n+1 n+2 n n n+1 address set dummy read data read n data read (n+1) wr rd column address bus holder figure 4.3 read timing
38 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 4.3 C 4.6 4.0 functional description 4.3 status flag the SED1560 series has a single bit status flag, d7. when d7 is high, the device is busy and will accept only a status read command. it is not necessary for the microprocessor to check the status of this bit before each command, if enough time is allowed for the last cycle to be completed. 4.4 display data ram the SED1560 series stores the display data sent from the microcomputer in the built-in display data ram (166 65 bits) and generates the lcd drive signals. it is a 166-column 65-row addressable array as shown in figure 4.4. the 65 rows are divided into 8 pages of 8 lines and a ninth page with a single line (d0 only). data is read from or written to the 8 lines of each page directly through d0 to d7. the microprocessor reads from and writes to ram through the i/o buffer. since the lcd controller oper- ates independently, data can be written to ram at the same time as data is being displayed, without causing the lcd to flicker. the time taken to transfer data is very short, because the microprocessor inputs d0 to d7 correspond to the lcd common lines as shown in figure 4.5. large display configuration can thus be created using mul- tiple SED1560 series devices. 4.5 column address counter the column address counter is an 8-bit presettable counter that provides the column address to display data ram. see figure 4.4. it is incremented by 1 each time a read or write command is received. the counter automatically stops at the highest address, a6h. the contents of the column address counter are changed by the column address set command. this counter is independent of the page address register. when the select adc command is used to select inverse display operation, the column address de- coder inverts the relationship between the ram col- umn data and the display segment outputs. 4.6 page address register the 4-bit page address register provides the page address to display data ram. the contents of the register are changed by the page address set com- mand. page address 8 (1000) is a special use ram area for the indicator.
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 39 174-3.0 4.0 functional description 4.6 d0 d1 d2 d3 d4 1 0 1 0 0 com0 com1 com2 com3 com4 figure 4.5 ram-to-lcd data transfer figure 4.4 display data ram addressing note: for 1/65 and 1/33 display duty cycles, page 9 is accessed follow- ing 1bh and 3bh, respectively. page address data column address line address common address d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 1 0 00h 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f to to to a2 a3 a4 a5 o3 o2 o1 o0 o162 o163 o164 o165 o0 o1 o2 o3 o4 o5 o6 o7 a5 a4 a3 a2 a1 a0 9f 9e o0 o1 o2 o3 o4 o5 o6 o7 do =0 do =1 adc lcd out 0 0 1 1 0 0 1 1 0 com 0 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com10 com11 com12 com13 com14 com15 com16 com17 com18 com19 com20 com21 com22 com23 com24 com25 com26 com27 com28 com29 com30 com31 com32 com33 com34 com35 com36 com37 com38 com39 com40 com41 com42 com43 com44 com45 com46 com47 com48 com49 com50 com51 com52 com53 com54 com55 com56 com57 com58 com59 com60 com61 com62 com63 com 1 page 0 page 1 page 2 page 3 page 4 page 5 page 6 page 7 page 8 1/64 1/32 start
40 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 4.7 C 4.8 4.0 functional description 4.7 initial display line register the initial display line register stores the address of the ram line that corresponds to the first (normally the top) line (com0) of the display. see figure 4.4. the contents of this 6-bit register are changed by the initial display line command. at the start of each lcd frame, synchronized with sync, the initial line is copied to the line counter. the line counter is then incremented on the cl clock signal once for every display line. this generates the line addresses for the transfer of the 166 bits of ram data to the lcd drivers. if a 1/65 or 1/33 display duty cycle is selected by the duty+1 command, the line address corresponding to the 65th or 33rd sync signal is changed and the indicator special-use line address is selected. if the duty+1 command is not used, the indicator special- use line address is not selected. the six different lcd driver arrangements. the necessary lcd driver voltage is automatically allocated to the com/seg dual outputs when their function is determined by the output selection circuit. the SED1560 selects case 1, 2 or 6 while the sed1561 selects case 3, 4, 5 or 6. the com/seg output status for the sed1562 is fixed and so cannot be selected. when com outputs are assigned to the output driv- ers, the unused ram area is not available. however, all ram column addresses can still be accessed by the microprocessor. since duty setting and output selection are inde- pendent, the appropriate duty must be selected for each case. cases 1 to 6 are determined according to the three lowest bits in the output status register in the output selection circuit. the com output scanning direction can be selected by setting bit d3 in the output status register to h or l. when the duty+1 command is executed, pin com1 becomes as shown in figure 4.4 irrel- evant to output selection. 4.8 output selection circuit the number of common (com) and segment (seg) driver outputs can be selected to fit different lcd panel configurations by the output selection circuit. there are 70 segment-only outputs (o32 to o101) and 96 common or segment dual outputs (o0 to o31 and o102 to o165). a command selects the status of the dual common/segment outputs. figure 4.6 shows figure 4.6 output configuration selection adc (d0) l h 0 165 165 0 column address display data ram 102 segments 64 commons 32 commons 32 commons 102 segments 32 commons 134 segments 32 commons 134 segments 134 segments 166 segments 150 segments 16 commons 16 commons 16 commons o0 o15 o31 o101 o133 o149 o165 case 1 case 2 case 3 case 4 case 5 case 6 sed1562
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 41 174-3.0 4.0 functional description 4.8 since master/slave operation and the output selec- tion circuit are completely independent in the SED1560 series, a chip on either the master or slave side can be allocated to the com output function in multi-chip configuration. the lcd driver outputs shown in table 4.5 become ineffective when the SED1560 or sed1561 is used with 1/48 or 1/24 duty, respectively. in this case, ineffective outputs are used in the open state. table 4.4 SED1560 sed1561 sed1562 duty 1/64 1/48 1/32 1/24 1/16 comi function com64 com48 com32 com24 com16 table 4.5 output status register ineffective output d3 d2 d1 d0 case 1 0101 o150 ~ o165 SED1560 1101 o102 ~ o117 case 2 0110 o150 ~ o165 1110 o16 ~ o31 case 3 0011 o0 ~ o7 1011 o23 ~ o31 sed1561 case 4 0010 o158 ~ o165 1010 o134 ~ o141 case 5 0001 o158 ~ o165 1001 o8 ~ o15
42 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 1/64 duty (display area 102 64) case status register lcd driver output d3 d2 d1 d0 o0 o31 o32 o101 o102 o133 o134 o165 1 0101 com0 com63 1101 com63 com0 2 0100 com31 com0 seg102 com32 com63 1100 com32 com63 seg102 com31 com0 6 0 0 0 seg166 4.9 SED1560 output status the SED1560 selects any output status from cases 1, 2 and 6. 4.9 C 4.10 4.0 functional description 1/48 duty (display area 102 48) case status register lcd driver output d3 d2 d1 d0 o0 o31 o32 o101 o102 o133 o134 o165 1 0101 com0 com47 1101 com47 com0 2 0100 com31 com0 seg102 com32 47 1100 com32 47 seg102 com31 com0 6 0 0 0 seg166 1/32 duty (display area 134 32) case status register lcd driver output d3 d2 d1 d0 o0 o15 o16 o31 o32 o133 o134 149 150 o165 3 0011 com31 com0 seg134 1011 com0 com31 seg134 4 0010 seg134 com0 com31 1010 seg134 com31 com0 5 0001 15 com0 seg134 com16 31 1001 com16 31 seg134 15 com0 6 0 0 0 seg166 4.10 sed1561 output status the sed1561 selects any output status from cases 3, 4, 5 and 6.
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 43 174-3.0 lcd driver output o0 o149 o150 o165 seg150 15 com0 4.0 functional description 4.10 C 4.12.3 4.11 sed1562 output status com/seg output status of the sed1562 is fixed. 1/16 duty (display area 150 16) 1/24 duty (display area 134 24) case status register lcd driver output d3 d2 d1 d0 o0 o15 o16 o31 o32 o133 o134 149 150 o165 3 0011 com23 com0 seg134 1011 com0 com23 seg134 4 0010 seg134 com0 com23 1010 seg134 com23 com0 5 000115 com0 seg134 16 23 100116 23 seg134 15 com0 6 0 0 0 seg166 4.12 display timers 4.12.1 line counter and display data latch timing the display clock, cl, provides the timing signals for the line counter and the display data latch. the ram line address is generated synchronously using the display clock. the display data latch synchronizes the 166-bit display data with the display clock. the timing of the lcd panel driver outputs is independent of the timing of the input data from the microprocessor. 4.12.2 fr and sync the lcd ac signal, fr, and the synchronization signal, sync, are generated from the display clock. the fr controller generates the timing for the lcd panel driver outputs. normally, 2-frame wave pat- terns are generated, but n -line inverse wave patterns can also be generated. these produce a high-quality display if n is based on the lcd panel being used. sync synchronizes the timing of the line counter and common timers. it is also needed to synchronize the frame period and a 50% duty clock. in a multiple-chip configuration, fr and sync are inputs. the sync signal from the master synchro- nizes the line counter and common timing of the slave. 4.12.3 common timing signals the internal common timing and the special-use common driver start signal, dyo, are generated from cl. as shown in figures 4.7 and 4.8, dyo outputs a high-level pulse on the rising edge of the cl clock pulse that precedes a change on sync. dyo is generated by both the SED1560 series devices, regardless of whether the device is in master or slave mode. however, when operating in slave mode, the device duty and the external sync signal must be the same as that of the master. in a multiple-chip configu- ration, fr and sync must be supplied to the slave from the master.
44 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 4.13 4.0 functional description table 4.6 master and slave timing signal status part number mode fr sync clo dyo master output output cl output output high slave input input imped- output ance 4.13 two-frame ac driver waveform (sed1561, 1/32 duty) 3132123456 27282930313212345 cl sync fr dyo com0 com1 ram data seg n v dd v1 v2 v3 v dd v1 v2 v3 v dd v2 v3 v5 figure 4.7 frame driver timing for duty 1/32 SED1560 series
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 45 174-3.0 4.0 functional description 4.14 4.14 n line inverse driver waveform ( n =5, line inverse register 4) 3132123456 27282930313212345 cl sync fr dyo com0 com1 ram data seg n v dd v1 v4 v5 v dd v1 v4 v5 v dd v2 v3 v5 note: when n = 5, the line inversion register is set to 4. figure 4.8 line inverse driver timing
46 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 4.15 C 4.20 4.0 functional description 4.15 display data latch display data is transferred from ram to the lcd drivers through the display data latch. this latch is controlled by the display on/off, display all points on/off and normal/inverse display commands. these commands do not alter the data. 4.16 lcd driver the lcd driver converts ram data into the 167 outputs that drive the lcd panel. there are 70 seg- ment outputs, 96 segment or common dual outputs, and a com1 output for the indicator display. two shift registers for the common/segment drivers are used to ensure that the common outputs are out- put in the correct sequence. the driver output volt- ages depend on the display data, the common scan- ning signal and fr. 4.17 display data latch circuit the display data latch circuit temporarily stores the output display data from the display data ram to the lcd driver circuit in each common period. since the normal/inverse display, display on/ off and display all points on/off commands control the data in this latch, the data in the display data ram remains unchanged. 4.18 lcd driver circuit this multiplexer generates 4-value levels for the lcd driver, having 167 outputs of 70 seg outputs, 96 seg/com dual outputs and a com output for the indicator display. the seg/com dual outputs have a shift register and sequentially transmit com scan- ning signals. the lcd driver voltage is output accord- ing to the combination of display data, com scanning signal and fr signal. figure 4.9 shows a typical seg/ com output waveform. 4.19 oscillator circuit the low power consumption type cr oscillator adjusting the oscillator frequency by use of only oscillator resistor r f is used as a display timing signal source or clock for the voltage raising circuit of the lcd power supply. the oscillator circuit is available only in the master operation mode. when a signal from the oscillator circuit is used for display clock, fix the cl pin to the v ss level. when the oscillator circuit is not used, fix the osc1 or osc2 pin to the v dd or v ss level, respectively. the oscillator signal frequency is divided and output from the cl0 pin as display clock. the frequency is divided to one-fourth, one-eighth, or one-sixteenth in the SED1560, sed1561, or sed1562, respectively. 4.20 fr control circuit the lcd driver voltage supplied to the lcd driver outputs is selected using fr signal.
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 47 174-3.0 4.0 functional description 4.20 figure 4.9 example of segment and common timing com0 com1 com2 com3 com4 com5 com6 com7 com8 com9 com10 com11 com12 com13 com14 com15 seg0 seg1 seg2 seg3 seg4 fr (sync) com0 com1 com2 seg0 seg1 com0 to seg0 com0 to seg1 v dd v ss v dd v1 v2 v3 v4 v5 v dd v1 v2 v3 v4 v5 v dd v1 v2 v3 v4 v5 v dd v1 v2 v3 v4 v5 v dd v1 v2 v3 v4 v5 v5 v4 v3 v2 v1 v dd ?1 ?2 ?3 ?4 ?5 v5 v4 v3 v2 v1 v dd ?1 ?2 ?3 ?4 ?5
48 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 4.21 C 4.22 4.0 functional description 4.21 power supply circuit the SED1560 series has an internal dc/dc con- verter to generate lcd bias voltages. the internal power supply circuit can be used only when the controller operates in master mode. the power circuit consists of a triple boosting circuit, a voltage regula- tion circuit and a low power voltage follower circuit. the power circuit built into SED1560 series is set for smaller scale liquid crystal panels and it is not suit- able when the picture element is larger or to drive a liquid crystal panel with larger indication capacity using multiple chips. it is recommended that an exter- nal power supply is used when using a liquid crystal panel with a larger load capacity. the power supply circuit can be controlled by the built- in power on/off command. when the built-in power is turned off, the boosting circuit, voltage regulation circuit and voltage follower circuit all go open. in this case, the liquid crystal driving voltage v1, v2, v3, v4 and v5 should be supplied from outside and the terminals cap1+, cap1C, cap2+, cap2C, v out and v r should be kept opened. various functions of the power circuit can be selected by combinations of the setting of the t1 and t2. it is also possible to make a combined use of the external power supply and a portion of the functions of the built- in power supply. when (t1, t2) = (h, l), the boosting circuit does not work and open the boosting circuit terminals (cap1+, cap1C, cap2+ and cap2C) and apply liquid crystal driving voltage to the v out terminals from outside. when (t1, t2) = (h, h), the boosting circuit and voltage regulation circuit do not work and open the boosting circuit terminals and the vr terminals and apply liquid crystal driving voltage to the v5, and leave the v out pin open. 4.22 tripler boosting circuit by connecting capacitors c1 between cap1+ and cap1C, cap2+ and cap2C and v ss C v out , the electric potential between v dd C v ss is boosted to the triple toward negative side and outputted from the v out terminal. when a double boosting is required, disconnect the capacitor between cap2+ and cap2C and short-circuit the cap2C and v out terminals to obtain output boosted to the double out of the v out (or cap2C) terminal. signals from the oscillation circuit are used in the boosting circuit and it then is necessary that the oscillation circuit is in operation. electric potentials by the boosting functions are shown in figure 4.10 and 4.11. table 4.7 voltage voltage external voltage voltage t1 t2 converter regulation v/f voltage converter regulation circuit circuit circuit input circuit terminals terminals ll o o o lh o o o hl x o o v out open h h x x o v5 open open
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 49 174-3.0 4.0 functional description 4.22 C 4.23 v dd = 0v v ss = ?v v out = 3 v ss = ?5v (v cc = +5v) v dd = 0v (gnd) v ss = ?v v out = 2 v ss = ?0v figure 4.10 electric potentials of double boosting figure 4.11 electric potentials of triple boosting 4.23 voltage regulation circuit (software contrast adjustment function is not used) r b r a ra v r v reg v dd v5 rb + figure 4.12 voltage regulation circuit the boosted voltage coming out from v out is ad- justed to become the liquid crystal driving voltage v5 via the voltage regulation circuit. v5 voltage can be regulated within a range of |v5| < |v out | by adjust- ment of resistors r a and r b and it may be calculated by the following equation: v5 = (1 + ) v reg equation 4.1 wherein v reg is the constant voltage source inside the ic and the voltage is constant at v reg ? 2.5v. voltage regulation of the v5 output is made by con- necting variable resistors between v r , v dd and v5. for fine adjustment of the v5 voltage, a combination of fixed resistors r1 and r3 and a variable resistor r2 is needed. examples of settings of r1, r2, and r3: ? r1 + r2 + r3 = 5 m w (determined by the current required to flow between v dd and v5) ? voltage variation range by r2: C11v ~ C13v (determined based on the characteristics of the liquid crystal being used) using the above conditions and equation 4.1, the following calculations can be made: r1 = 0.947 m w r2 = 0.174 m w r3 = 3.879 m w the voltage regulation circuit renders a temperature gradient, after v reg output, of about C0.17% / c, but when any other temperature gradient is needed, connect a thermistor in series with the output voltage regulating resistors. since the vr terminal has a high input impedance, it is necessary to take some noise suppression mea- sures, such as using the shortest length wiring or shielded wiring.
50 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 4.24 4.0 functional description 4.24 voltage regulation circuit using software contrast adjustment control function by using software contrast adjustment control function, it is possible to control the liquid crystal driving voltage v5 by inputting corresponding commands to adjust the contrast of the liquid crystal display. with such an electronic contrast control function, setting 5-bit data to the electronic contrast control register will make available 32 states of voltages from which one voltage level can be selected for the liquid crystal driving voltage v5. when using the software contrast control function, it is necessary to execute built-in power supply on command after one of (t1, t2) = (l, l), (t1, t2) = (l, h), or (t1, t2) = (h, l) is set. example of constant setting when using the software contrast adjustment control function (1) determine a v5 voltage setting range by the electronic contrast control. liquid crystal driving voltage ...........................v5 C 10v max. to C15v min. v5 variable voltage width ................................ 4v (2) determine r b . r b = v5 variable voltage width / i ref (32 states i ref ? 6.5 m a constant-current value) r b = 4v / 6.5 m a (16 states i ref ? 3.2 m a constant-current value) = 615 k w (3) determine r a . r a = v reg (for v reg and v5 set voltage, absolute values are used.) (v5 set voltage max C v reg ) / r b r a = 2.5v (10v C 2.5v) / 615 w = 205 k w (4) adjust r a . set the electronic contrast control register value to (d4, d3, d2, d1, d0) = (1, 0, 0, 0, 0) or (0, 1, 1, 1, 1), and adjust the r a value to the optimum contrast. to set the voltage value by the software contrast adjustment control to the 16 states, fix the data d4 of the electronic contrast control register to l and set data in d3 to d0. at this time, set i ref ? 3.2 m a and determine r a and r b according to the above steps (1) to (4). because i ref is a simplified constant-current source, it is necessary to consider the variation of maximum 40% as manufacturing dispersion. the temperature dependency of i ref becomes d i ref ? C0.0525 m a/ c (in the variable voltage 32 states) or d i ref ? C0.0234 m a/ c (variable voltage 16 states). determine r a and r b for the lcd to be used, by taking the above dispersion and variations due to temperatures into consideration. when using the software contrast adjustment control function, r a must be a variable resistance and the
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 51 174-3.0 optimum contrast adjustment described in (4) must be made for each ic chip in order to compensate the v5 voltage value due to the dispersion of v reg and i ref . when the contrast control function is not used, set the register value to (d4, d3, d2, d1, d0) = (0, 0, 0, 0, 0) by the res signal or electronic contrast control register set command. 4.25 precautions on using the SED1560 series software contrast adjustment control function the SED1560 series is provided with a software contrast adjustment control function having up to 32 levels to control the regulator. the v5 voltage, when the software contrast control function is used, is represented by the following expression: v5 = (1 + r b / r a ). v reg + r b d i ref by this expression, the software contrast control function controls an increment of v5 voltage by means of the current source i ref built into the ic. (in the case of 32 levels, d i ref = i ref / 32). the v5 minimum voltage is set by the resistance ratio of the externally-installed r a and r b , and the voltage step width by the software contrast control is determined by the resistance value of r b . the reference voltage v reg and current source i ref built into the SED1560 series are kept constant against voltage variations. however, ic manufacturing dispersion and variations due to temperatures are caused as shown below. v reg = 2.5v 0.15v v reg = C0.17%/ c i ref = 3.2 m a 40% (for 16 levels) i ref = C0.0234 m a/ c 6.5 m a 40% (for 32 levels) i ref = C0.0525 m a/ c example of constant setting conditions: center value ............................. v dd C v5 = 8.5v variable voltage width ............... 3.2v variable voltage level................ 32 levels (1) determination of r b . r b = v5 variable voltage width / i ref = 3.2v / 6.5 m a = 492 k w 4.0 functional description 4.24 C 4.25 rb v r v reg v dd v5 ra +
52 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 4.25 4.0 functional description (2) determination of r a . r a = v reg (v5 minimum set voltage C v reg ) / r b = 2.5v {(8.5v C 3.2v/2) C 2.5v} / 492k w = 280 k w (3) temperature dependency of v5 when v reg = 2.5v and i ref = 6.5 m a (32 levels). v5 minimum set voltage (v5 min) = 8.5v C 3.2v/2 = 6.9v t a = 25 c v5 max = v5 minimum set voltage + r b i ref = 6.9v + 492k w 6.5 m a = 10.1v ....................................... 1 v5 typ = (v5 max + v5 min) / 2 = (10.1v + 6.9v) / 2 = 8.5v ......................................... 2 t a = C10 c v5 min = (1 + r b / r a ) v reg (t a = C10 c) = (1 + 492k w / 280k w ) 2.5v {1 + (C0.17%/ c) (C10 c C 25 c)} = 7.3v ......................................... 3 v5 max = v5 min + r b i ref (t a = C10 c) = 7.3v + 492k w {6.5 m a + (C0.0525 m a/ c) (C10 c C 25 c)} = 11.4v ....................................... 4 v5 typ = (v5 max + v5 min) / 2 = (11.4v + 7.3v) / 2 = 9.35v ....................................... 5 t a = 50 c v5 min = (1 + r b / r a ) v reg (t a = 50 c) = (1 + 492k w / 280k w ) 2.5v {1 + (C0.17%/ c) (50 c C 25 c)} = 6.6v ......................................... 6 v5 max = v5 min + r b i ref (t a = 50 c) = 6.6v + 492k w {6.5 m a + (C0.0525 m a/ c) (50 c C 25 c)} = 9.15v ....................................... 7 v5 typ = (v5 max + v5 min) / 2 = (9.15v + 6.6v) / 2 = 7.9v ......................................... 8
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 53 174-3.0 ? to set the number of variable voltage levels to 16, specify i ref = 3.2 m a. ? margin calculation is performed by considering the dispersion of v reg and v ref according to the same procedure as (3). from this margin calculation, it is made clear that the center value of v5 is affected by variations of v reg and i ref . ? accordingly, it is necessary to set the electronic contrast control register value to (d4, d3, d2, d1, d0) = (1, 0, 0, 0, 0) or (0, 1, 1, 1, 1) and adjust the r a value to the optimum contrast. ? the voltage step width by the electronic contrast control is changed by the dispersion of i ref . it is necessary to consider that supposing that 0.2v/step is set by typ value, the maximum variation of 0.12v to 0.28v occurs. * * 4 5 3 8 7 6 1 2 * v5 max v5 typ v5 min ?0 14 12 10 8 6 4 2 0 100 102030405060 (?) ta (v) v5 sed 1560 series * example of v5 voltage when using SED1560 series electronic contrast control 4.0 functional description 4.25
54 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 since the i ref is a simplified constant current source, when using the electronic contrast control function, it becomes necessary to make adjustment to the opti- mum contrast as given in the above item (4), with each of the ic chips, using the r a as a variable resistor. when not using the software contrast adjustment control function, set the register to (d3, d2, d1, d0) = (0, 0, 0, 0) using the res signal or by means of the software contrast adjustment control register set- ting command. 4.26 liquid crystal voltage generating circuit a v5 potential is resistively divided within the ic to cause v1, v2, v3 and v4 potentials needed for driving of liquid crystals. the v1, v2, v3 and v4 potentials are further converted in the impedance by the voltage follower before being supplied to the liquid crystal driving circuit. the liquid crystal driving voltage is fixed with each type (see table 4.8). as shown in figure 4.13, it needs to connect, exter- nally, 5 units of voltage stabilizing capacitors c2 to the liquid crystal power terminals. when selecting such capacitor c2, make actual liquid crystal displays matching to the display capacity of the liquid crystal display panel, before determining the capacitance as the constant value for voltage stabilization. 4.25 C 4.26 4.0 functional description table 4.8 type liquid crystal driving voltage SED1560 1/9 of the bias voltage sed1561 1/7 of the bias voltage sed1562 1/5 of the bias voltage table 4.9 reference setting value reference set values: SED1560 ..... v5 ? C11 ~ C13v sed1561 ..... v5 ? C7 ~ C9v sed1562 ..... v5 ? C5 ~ C7v (variable) SED1560 sed1561 sed1562 c1 0.47 m f~ 0.47 m f~ 0.47 m f~ c2 1.0 m f~ 0.47 m f~ 0.47 m f~ 1.0 m f~ 0.47 m f~ 0.47 m f~ r1 1m w 700k w 500k w r2 200k w 200k w 200k w r3 4m w 1.6m w 700k w lcd 32 51 16 67 8 75 size mm mm mm dot 64 102 32 134 16 150
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 55 174-3.0 *1 connect oscillator feedback resistor r f as short as possible and place it close to the ic for preventing a malfunction. *2 use short wiring or shielded cables for the v r pin due to high input impedance. *3 determine c1 and c2 depending on the size of the lcd panel driven. you must set these values so that the lcd driving volt- age becomes stable. set (t1, t2) = (h, l) and supply an external voltage to v out . display the lcd heavy load pattern and determine c2 so that the lcd driving voltages (v1 to v5) become stable. how- ever, it is necessary to make every c2 capacitance value equal. then, set (t1, t2) = (l, l) and determine c1. *4 the lcd size indicates the vertical and horizontal length of the lcd panel display area. figure 4.14 when external lcd power supply is used 4.0 functional description 4.26 rf v dd v ss cap1+ cap1 cap2+ cap2 v out v5 v r v dd v1 v2 v3 v4 v5 osc1 osc2 m/s sed156x external supply voltage figure 4.13 when the built-in power supply is used rf *1 v dd v ss v ss cap1+ cap1 cap2+ cap2 v out v5 v r v dd v1 v2 v3 v4 v5 r1 r3 r2 *2 c1 c1 c1 cl c2 osc1 osc2 m/s sed156x
56 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 4.27 4.0 functional description 4.27 reset when power is turned on, the SED1560 series is initialized on the rising edge of res. initial settings are as follows: 1. display : off 2. display mode : normal 3. n -line inversion : off 4. duty cycle : 1/64 5. adc select : normal 6. read/write modify : off 7. on-chip power supply : off 8. serial interface register : cleared 9. display initial line register : line 1 10. column address counter : 0 11. page address register : page 0 12. output selection circuit : case 6 13. n -line inversion register : 16 14. software contrast setting : zero the res pin should be connected to the microproces- sor reset terminal so that both devices are reset at the same time. res must be low for at least 1 m s to correctly reset the SED1560 series. normal opera- tion starts 1 m s after the rising edge on res. if the SED1560 series is not properly initialized when power is turned on, it can lock itself into a state that cannot be cancelled. when the reset command is used, only initial set- tings 9 to 14 are active.
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 57 174-3.0 5.0 commands
58 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 this page intentionally blank
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 59 174-3.0 5.0 commands 5.1 normally not needed, commands can be processed at high speed. when the serial interface is used, the order of data entry is d7 to d0. table 5.1 command code description a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 turns the display on and off. display on/off 0101010111dd = 0 off d = 1 on initial display line 01001 display line address sets the display ram line address for com0. page address set 0101011 page address sets the ram page address register. column address set 0100001 column address sets the column address register upper (upper four bits) upper four bits four bits. column address set 0100000 column address sets the column address register lower (lower four bits) lower four bits four bits. read status 0 0 1 status 0000 reads out status information. write display data 1 1 0 write data writes to display ram. read display data 1 0 1 read data reads from display ram. select adc 0101010000d sets the display ram segment output. d = 0 normal d = 1 inverse normal/inverse 0101010011d sets the lcd display mode. display d = 0 normal d = 1 inverse display all points sets the segments display mode. on/off 0101010010dd = 0 normal d = 1 all display segments on select duty 0101010100d sets the lcd controller duty (1). d = 0, d=1 see table 5.3 duty + 1 0101010101d sets the lcd controller duty (2). d = 0 normal d = 1 duty + 1 set n -line inversion 0100011 number of sets the number of inverted lines in the in- inverted items version register for the inversion controller. cancel n -line inversion 01000100000 cancels line inversion display mode. sets modified read mode. the column read modify write 01011100000 address counter is not incremented when reading. end 01011101110 cancels modified read mode. power-on 01011101101 completes the turn-on sequence of built- completion in power supply reset 01011100010 resets the internal registers. output status set 0101100 output status sets the common and segment output status register. lcd power supply 0100010010d turns the power supply on and off. on/off d = 0 off d = 1 on software contrast setting the v5 output voltage to the elec- setting 010100 tronic contrast control register. power save a complex command to turn off the display and light all indicators. electronic contrast control resistance value 5.1 command summary a0, rd and wr identify the data bus commands. interpretation and execution of commands are syn- chronized to the internal clock. since a busy check is
60 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 5.2 C 5.2.4 5.2 command definitions 5.2 command definitions 5.2.1 display on/off alternately turns the display on and off. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101010111d note: d = 0 display off d = 1 display on 5.2.2 initial display line loads the ram line address of the initial display line, com0, into the initial display line register. the ram display data becomes the top line of the lcd screen. it is followed by the higher number lines in ascending order, corresponding to the duty cycle. the screen can be scrolled using this command by incrementing the line address. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01001a5a4a3a2a1a0 a5 a4 a3 a2 a1 a0 line address 000000 0 000001 1 000010 2 111110 62 111111 63 5.2.3 page address set loads the ram page address from the microproces- sor into the page address register. a page address, along with a column address, defines a ram location for writing or reading display data. when the page address is changed, the display status is not affected. page address 8 is a special use ram area for the indicator. only d0 is available for data exchange. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101011a3a2a1a0 a3 a2 a1 a0 page 00000 00011 00102 00113 01004 01015 01106 01117 10008 5.2.4 column address set loads the ram column address from the micropro- cessor into the column address register. the column address is divided into two parts4 high-order bits and 4 low-order bits. when the microprocessor reads or writes display data to or from ram, column addresses are auto- matically incremented, starting with the address stored in the column address register and ending with address 166. the page address is not incremented automatically. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0100001a7a6a5a4 r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0100000a3a2a1a0 a7 a6 a5 a4 a3 a2 a1 a0 column address 00000000 0 00000001 1 10100101 165
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 61 174-3.0 5.2 command definitions 5.2.5 C 5.2.9 5.2.7 read display data sends bytes of display data to the microprocessor from the ram location specified by the column ad- dress and page address registers. the column ad- dress is incremented automatically so that the micro- processor can continuously read data from the ad- dressed page. a dummy read is required after loading an address into the column address register. display data cannot be read through the serial interface. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 0 1 read data 5.2.8 select adc selects the relationship between the ram column addresses and the segment drivers. when reading or writing display data, the column address is incremented as shown in figure 5.4. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101010000d note: d = 0 rotate right (normal direction) d = 1 rotate left (reverse direction) the output pin relationship can also be changed by the microprocessor. there are very few restrictions on pin assignments when constructing an lcd module. 5.2.9 normal/inverse display determines whether the data in ram is displayed normally or inverted. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101010011d note: d = 0 lcd segment is on when ram data is 1 (normal). d = 1 lcd segment is on when ram data is 0 (inverse). 5.2.5 read status indicates to the microprocessor the SED1560 series status conditions. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 001 busy adc on/ re- 0000 off set ? busy - indicates whether or not the SED1560 series will accept a command. if busy is 1, the device is currently executing a command or is resetting, and no new commands can be accepted. if busy is 0, a new command can be accepted. it is not necessary for the microprocessor to check the status of this bit if enough time is allowed for the last cycle to be completed. ? adc - indicates the relationship between ram column addresses and the segment drivers. if adc is 1, the relationship is normal and column address n corresponds to segment driver n . if adc is 0, the relationship is inverted and column address (165 C n ) cor- responds to segment driver n . ? on/off - indicates whether the display is on or off. if on/off is 1, the display is off. if on/off is 0, the display is on. note that this is the opposite of the display on/off command. ? reset - indicates whether initialization is in process as the result of res or the reset command. 5.2.6 write display data writes bytes of display data from the microproces- sor to the ram location specified by the column address and page address registers. the column address is incremented automatically so that the microprocessor can continuously write data to the addressed page. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 write data
62 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 5.2.10 display all points on/off turns all lcd points on independently of the display data in ram. the ram contents are not changed. this command has priority over the normal/inverse display command. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101010010d note: d = 0 normal display status d = 1 all display segments on if this command is received when the display status is off, the power save command is executed. 5.2.11 select duty selects the lcd driver duty. since this is independent from the contents of the output status register, the duty must be selected according to the lcd output status. in multi-chip configuration, the master and slave de- vices must have the same duty. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101010100d table 5.2 model d duty SED1560 0 1/48 1 1/64 sed1561 0 1/24 1 1/32 sed1562 0 1/16 1 1/16 5.2.12 duty + 1 increases the duty by 1. if 1/48 or 1/64 duty is selected in the SED1560, for example, 1/49 or 1/65 is set, respectively, and com1 functions as either the com48 or com64 output. the display line always accesses 5.2.10 C 5.2.14 5.2 command definitions the ram area corresponding to page address 8, d0. (refer to figure 5.4.) in multi-chip configuration, the duty + 1 command must be executed to both the master and slave sides. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101010101d table 5.3 model d duty SED1560 0 1/48 or 1/64 1 1/49 or 1/65 sed1561 0 1/24 or 1/32 1 1/25 or 1/33 sed1562 0 1/16 1 1/17 5.2.13 set n -line inversion selects the number of inverse lines for the lcd ac controller. the value of n is set between 2 and 16 and is stored in the n -line inversion register. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0100011a3a2a1a0 a3 a2 a1 a0 number of inverted lines 0000 0001 2 0010 3 1110 15 1111 16 5.2.14 cancel n -line inversion cancels n -line inversion and restores the normal 2- frame ac control. the contents of the n -line inversion register are not changed. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01000100000
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 63 174-3.0 5.2 command definitions 5.2.15 C 5.2.17 5.2.15 modify read following this command, the column address is no longer incremented automatically by a read display data command. the column address is still incremented by the write display data command. this mode is cancelled by the end command. the column address is then returned to its value prior to the modify read command. this command makes it easy to manage the duplication of data from a particu- lar display area for features such as cursor blinking. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100000 note: the column address set command cannot be used in modify-read mode. 5.2.16 end cancels the modify read mode. the column address prior to the modify read command is restored. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011101110 5.2.17 reset resets the initial display line, column address, page address, and n -line inversion registers to their initial values. this command does not affect the display data in ram. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01011100010 the reset command does not initialize the lcd power supply. only hardware res can be used to initialize the power supplies. figure 5.1 command sequence for cursor blinking page address set column address set read?odify?rite cycle dummy read data read data write changes finished? end no yes figure 5.2 column address read?odif y ?rite mode set n n+1 n+2 n+3 n+m n return end
64 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 5.2.20 lcd power supply on/off turns the SED1560 series lcd power supply on or off. when the power supply is on, the voltage converter, the voltage regulator circuit and the volt- age followers are operating. in order for the converter to function, the oscillator must also be operating. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 01000100100 2 4 off note: d = 0 supply off (24h) d = 1 supply on (25h) when an external power supply is used with the SED1560 series, the internal supply must be off. if the SED1560 series is used in a multiple-chip configuration, an external power supply that meets the specifications of the lcd panel must be used. an SED1560 series operating as a slave must have its internal power supply turned off. 5.2.18 C 5.2.20 5.2 command definitions 5.2.18 output status set selects the common or segment output state of the lcd driver dual outputs. the a3 bit selects the scan direction of the outputs. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101100a3a2a1a0 5.2.19 output status register available only in the SED1560 and sed1561. this command selects the role of the com/seg dual pins and determines the lcd driver output status. the com output scanning direction can be selected by setting a3 to h or l. for details, refer to the output status circuit in each function description. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 0101100a3a2a1a0 a3: selection of the com output scanning direction table 5.4 output number of a2 a1 a0 status com/seg remarks output pins 0 0 0 case 6 seg 166 0 0 1 case 5 seg 134, com 32 0 1 0 case 4 seg 134, com 32 0 1 1 case 3 seg 134, com 32 1 0 0 case 2 seg 102, com 64 1 0 1 case 1 seg 102, com 64 1 1 0 case 6 seg 166 1 1 1 case 6 seg 166 applies to the SED1560 applies to the SED1560/61 applies to the sed1561 applies to the SED1560/61 sequence in the built-in power on/off status to turn on internal power supply, execute the follow- ing built-in power supply on sequence. to turn off internal power supply, execute the power save se- quence as shown in the following power supply off status. accordingly, to turn on internal power supply again after turn it off (power save), execute the power save clear sequence that is described below.
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 65 174-3.0 sequence in the power save status power save and power save clear must be executed according to the following sequence. to give a liquid crystal driving voltage level by the externally-installed resistance dividing circuit, the current flowing in this resistance must be cut before or concurrently with putting the SED1560 series into the power save status so that it may be fixed to the floating or v dd level. when using an external power supply, likewise, its function must be stopped before or concurrently with putting the SED1560 series into the power save status so that it may be fixed to the floating or v dd level. in a configuration in which an exclusive common driver such as sed1630 is combined with the SED1560 series, it is necessary to stop the external power supply function after putting all the common output into non-selection level. power save sequence power save clear sequence output status select internal power supply on (waiting time) power supply startup end *duty+1 *3 *6 *1 *5 *2 command command command command c*(h) 25(h) ed(h) display all on status off ab(h) *2 *3 *1 command command command ae(h) aa(h) command a5(h) cf(h) display off *duty+1 clear display all on output status case 6 *1. in the power save sequence, the power save status is provided after the display all on command. in the power save clear se- quence, the power save status is cleared after the display all on status off com- mand. *2. when the comi pin is not used, it is not necessary to enter the duty + 1 command and duty + 1 clear command. *3. in the sed1562, it is not necessary to ex- ecute a command to decide an output sta- tus. *4. the display on command can be executed anywhere if it is later than the display all on status off command. *5. when internal power supply startup end command is not executed, current is con- sumed stationarily. internal power supply startup end command must always be used in a pair with internal power supply on command. *6. the waiting time depends on the externally- installed capacitance c2 (refer to table 5.9). after the waiting time shown in the graph above (see bottom of previous page), the power supply can be started surely. 5.2 command definitions 5.2.20
66 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 internal power supply on status internal power supply off status reset by res signal output status select internal power supply on (waiting time) power supply startup end *duty+1 *1 *4,5 *3 *2 command command command command a*(h) 25(h) ed(h) ab(h) *2 command command command ae(h) aa(h) command a5(h) cf(h) display off *duty+1 clear display all on output status case 6 *1. regarding the sed1562, it is not neces- sary to execute a command to decide an output status. *2. when the comi pin is not used, it is not necessary to enter the duty + 1 and duty + 1 clear commands. *3. when the built-in power supply startup end command is not executed, current is consumed stationarily. internal power sup- ply startup end command must always be used in a pair with internal power supply on command. *4. the waiting time depends on the externally- installed capacitance c2 (refer to table 5.9). after the waiting time shown in the graph below, the power supply can be started surely. *5. within the waiting time in internal power supply on status, any command other than internal power supply control commands such as power save, and display on/off command, display normal rotation/reverse command, display all on command, output status select command and duty + 1 clear command can accept another command without any problem. ram read and write operations can be freely performed. 5.2.20 5.2 command definitions 1/5 bias 1/7 bias 1/9 bias 120 100 80 60 40 20 0 0.5 1.0 capacitance c2 (?) (ms) waiting time v5 voltage conditions 1/9 bias v5 = ?.0 to ?6.0 v 1/7 bias v5 = ?.0 to ?2.0 v 1/5 bias v5 = ?.5 to ?.0 v
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 67 174-3.0 5.3 software contrast control register 5.3 C 5.3.2 5.3 software contrast control register through these commands, the liquid crystal driving voltage v5 is output from the voltage regulation circuit of the built-in liquid crystal power supply, in order to adjust the contrast of the liquid crystal display. by setting data to the 5-bit register, one of the 32 voltage statuses may be selected for the liquid crystal driving voltage v5. external resistors are used for setting the voltage regulation range of the v5. for details refer to the paragraph of the voltage regulation circuit in the clause for the explanation of functions. r/w a0 rd wr d7 d6 d5 d4 d3 d2 d1 d0 010100a4a3a2a1a0 a4 a3 a2 a1 a0 | v5 | 00000 small (as the absolute value) 11111 large (as the absolute value) when not using the electronic contrast control func- tion, set to (0, 0, 0, 0). 5.3.1 power save (complex command) if the display all points on command is specified in the display off state, the system enters the power save status, reducing the power consumption to ap- proximate the static power consumption value. the internal state in the power save status is as follows: (a) the oscillator and power supply circuits are stopped. (b) the lcd driver is stopped and segment and common driver outputs output the v dd level. (c) an input of an external clock is inhibited and osc2 enters the high-impedance state. (d) the display data and operation mode be- fore execution of the power save com- mand are held. (e) all lcd driver voltages are fixed to the v dd level. the power save mode is cancelled by entering either the display on command or the display all points off command (display operation state). when exter- nal voltage driver resistors are used to supply the lcd driver voltage level, the current through them must be cut off by the power save signal. if an external power supply is used, it must be turned off using the power save signal in the same manner, and voltage levels must be fixed to the floating or v dd level. 5.3.2 connection between lcd drivers the lcd display area can be increased by using the SED1560 series in a multiple-chip configura- tion or with the SED1560 series special common driver (sed1630). figure 5.3 application with external driver: sed156x C sed1630 sed1630 fr fr sync m/s osc1 osc2 cl clo dyo rf yscl dio sed156x (master) v dd v ss
68 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 5.3.2 5.3 electronic contrast control register rf v ss v ss fr sync m/s osc1 osc2 cl clo dyo sed156x (slave) v ss osc1 osc2 cl clo dyo rf fr sync v ss v dd sed156x (master) m/s v ss fr sync m/s osc1 osc2 cl clo dyo sed156x (slave) osc1 osc2 cl clo dyo fr sync v dd sed156x (master) m/s v dd figure 5.4 sed156x C sed156x (when oscillator circuit is used) figure 5.5 sed156x C sed156x (external clock) v ss v ss fr sync m/s osc1 osc2 cl clo dyo sed156x (slave) osc1 osc2 cl clo dyo fr sync v dd sed156x (master) m/s v dd external clock v ss
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 69 174-3.0 5.4 microprocessor interface 5.4 microprocessor can be minimized by using a serial interface. when used in a multiple-chip configuration, the SED1560 series is controlled by the chip select signals from the microprocessor. figure 5.6 8080-series microprocessors figure 5.7 6800-series microprocessors v dd v ss v cc gnd mpu c86 a0 cs1 cs2 d0 to d7 rd wr res sed156x p/s a0 a0 to a7 iorq d0 to d7 rd wr res decoder reset v dd v ss v cc gnd mpu c86 a0 cs1 cs2 d0 to d7 e r/w res sed156x p/s a0 a0 to a15 vma d0 to d7 e r/w res decoder reset 5.4 microprocessor interface the SED1560 series communicates with a high- speed microprocessor, such as the intel 80xx family or the motorola 68xx family, through 8-bit parallel data transfer. the number of connections to the
70 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 5.4 C 5.5 5.4 microprocessor interface figure 5.8 serial interface v dd v ss v cc gnd mpu c86 a0 cs1 cs2 si scl res sed156x p/s a0 a0 to a7 port1 port2 res decoder reset v dd or gnd 5.5 lcd panel interface examples figure 5.9 single-chip configurations 65 102 commons SED1560 (master) case 1 segments 33 134 commons sed1561 (master) case 4 segments 17 150 commons sed1562 segments
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 71 174-3.0 5.5 lcd panel interface examples 5.5 figure 5.10 multiple-chip combinations commons SED1560 (master) case 1 segments commons sed1561 (master) case 4 segments segments SED1560 (slave) case 6 segments 65 268 33 300 case 6 sed1561 (slave)
72 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 5.6 5.6 special common driver configurations 5.6 special common driver configurations figure 5.11 special common driver configurations SED1560 (master) case 6 segments 65 166 sed1630 commons SED1560 (slave) case 6 segments 128 166 sed1631 commons commons segments SED1560 (master) case 6
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 73 174-3.0 6.0 packaging
74 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 this page intentionally blank
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 75 174-3.0 6.0 pad layout 6.1 figure 6.1 pad layout v5 v4 v3 v2 v1 v dd v r v5 v out cap2 cap2+ cap1 cap1+ v ss t1 t2 osc1 osc2 cl fr sync clo dyo d7 d6 d5 d4 d3 d2 d1 d0 v ss rd wr a0 c86 cs2 cs1 p/s si scl res m/s v dd v1 v2 v3 v4 v5 o46 o120 o121 o165 com1 o45 o0 sed156x chip size pad pitch chip thickness : : : 8.08 5.28 mm 100 ? (min) 625 ? ?25 ? 6.1 pad layout
76 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 6.1 6.0 pad layout table 6.1 SED1560 series pad center coordinates pad pin xy no. name 1 v5 3640 2487 2 v4 3489 2487 3 v3 3339 2487 4 v2 3188 2487 5 v1 3037 2487 6v dd 2889 2487 7 m/s 2755 2487 8 res 2604 2487 9 scl 2453 2487 10 si 2302 2487 11 p/s 2151 2487 12 cs1 2001 2487 13 cs2 1850 2487 14 c86 1699 2487 15 a0 1548 2487 16 wr 1397 2487 17 rd 1247 2487 18 v ss 1077 2487 19 d0 945 2487 20 d1 794 2487 21 d2 643 2487 22 d3 493 2487 23 d4 342 2487 24 d5 191 2487 25 d6 40 2487 26 d7 C111 2487 27 dyo C261 2487 28 clo C412 2487 29 sync C563 2487 30 fr C714 2487 31 cl C865 2487 32 osc2 C1015 2487 33 osc1 C1166 2487 34 t2 C1317 2487 35 t1 C1468 2487 36 v ss C1638 2487 37 cap1+ C1789 2487 38 cap1C C1939 2487 39 cap2+ C2090 2487 40 cap2C C2241 2487 41 v out C2392 2487 42 v5* C2543 2487 43 vr C2674 2487 44 v dd C2844 2487 45 v1 C2995 2487 46 v2 C3146 2487 47 v3 C3297 2487 48 v4 C3447 2487 49 v5 C3598 2487 50 o0 C3887 2294 51 o1 C3887 2194 52 o2 C3887 2094 53 o3 C3887 1994 54 o4 C3887 1894 55 o5 C3887 1794 56 o6 C3887 1694 57 o7 C3887 1594 58 o8 C3887 1494 59 o9 C3887 1394 60 o10 C3887 1294 61 o11 C3887 1194 62 o12 C3887 1094 63 o13 C3887 994 64 o14 C3887 894 65 o15 C3887 794 66 o16 C3887 694 67 o17 C3887 594 68 o18 C3887 494 69 o19 C3887 394 70 o20 C3887 294 71 o21 C3887 194 72 o22 C3887 94 73 o23 C3887 C6 74 o24 C3887 C106 75 o25 C3887 C206 76 o26 C3887 C306 77 o27 C3887 C406 78 o28 C3887 C506 79 o29 C3887 C606 80 o30 C3887 C706 81 o31 C3887 C806 82 o32 C3887 C906 83 o33 C3887 C1006 84 o34 C3887 C1106 85 o35 C3887 C1206 86 o36 C3887 C1306 87 o37 C3887 C1406 88 o38 C3887 C1506 89 o39 C3887 C1606 90 o40 C3887 C1706 91 o41 C3887 C1806 92 o42 C3887 C1906 93 o43 C3887 C2006 94 o44 C3887 C2106 95 o45 C3887 C2206 96 o46 C3711 C2487 97 o47 C3611 C2487 98 o48 C3511 C2487 99 o49 C3411 C2487 100 o50 C3311 C2487 101 o51 C3211 C2487 102 o52 C3111 C2487 103 o53 C3011 C2487 104 o54 C2911 C2487 105 o55 C2811 C2487 106 o56 C2711 C2487 107 o57 C2611 C2487 108 o58 C2511 C2487 109 o59 C2411 C2487 110 o60 C2311 C2487 111 o61 C2211 C2487 112 o62 C2111 C2487 113 o63 C2011 C2487 114 o64 C1911 C2487 115 o65 C1811 C2487 116 o66 C1711 C2487 117 o67 C1611 C2487 118 o68 C1511 C2487 119 o69 C1411 C2487 120 o70 C1311 C2487 121 o71 C1211 C2487 122 o72 C1111 C2487 123 o73 C1011 C2487 124 o74 C911 C2487 125 o75 C811 C2487 126 o76 C711 C2487 127 o77 C611 C2487 128 o78 C511 C2487 129 o79 C411 C2487 130 o80 C311 C2487 131 o81 C211 C2487 132 o82 C111 C2487 133 o83 C11 C2487 134 o84 89 C2487 135 o85 189 C2487 136 o86 289 C2487 137 o87 389 C2487 138 o88 489 C2487 139 o89 589 C2487 140 o90 689 C2487 141 o91 789 C2487 142 o92 889 C2487 143 o93 989 C2487 144 o94 1089 C2487 145 o95 1189 C2487 146 o96 1289 C2487 147 o97 1389 C2487 148 o98 1489 C2487 149 o99 1589 C2487 150 o100 1689 C2487 151 o101 1789 C2487 152 o102 1889 C2487 153 o103 1989 C2487 154 o104 2089 C2487 155 o105 2189 C2487 156 o106 2289 C2487 157 o107 2389 C2487 158 o108 2489 C2487 159 o109 2589 C2487 160 o110 2689 C2487 161 o111 2789 C2487 162 o112 2889 C2487 163 o113 2989 C2487 164 o114 3089 C2487 165 o115 3189 C2487 166 o116 3289 C2487 167 o117 3389 C2487 168 o118 3489 C2487 169 o119 3589 C2487 170 o120 3689 C2487 171 o121 3887 C2206 172 o122 3887 C2106 173 o123 3887 C2006 174 o124 3887 C1906 175 o125 3887 C1806 176 o126 3887 C1706 177 o127 3887 C1606 178 o128 3887 C1506 179 o129 3887 C1406 180 o130 3887 C1306 181 o131 3887 C1206 182 o132 3887 C1106 183 o133 3887 C1006 184 o134 3887 C906 185 o135 3887 C806 186 o136 3887 C706 187 o137 3887 C606 188 o138 3887 C506 189 o139 3887 C406 190 o140 3887 C306 191 o141 3887 C206 192 o142 3887 C106 193 o143 3887 C6 194 o144 3887 94 195 o145 3887 194 196 o146 3887 294 197 o147 3887 394 198 o148 3887 494 199 o149 3887 594 200 o150 3887 694 201 o151 3887 794 202 o152 3887 894 203 o153 3887 994 204 o154 3887 1094 205 o155 3887 1194 206 o156 3887 1294 207 o157 3887 1394 208 o158 3887 1494 209 o159 3887 1594 210 o160 3887 1694 211 o161 3887 1794 212 o162 3887 1894 213 o163 3887 1994 214 o164 3887 2094 215 o165 3887 2194 216 comi 3887 2294 pad pin xy no. name pad pin xy no. name pad pin xy no. name * one v5 output is used for the lcd driver supply voltage; the other is used for the electronic volume control.
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 77 174-3.0 6.2 SED1560 series tab pin layout 6.2 6.2 SED1560/1/2 tab pin layout figure 6.2 SED1560 series tab pin layout sed156x top view v5 v4 v3 v2 v1 v dd v r v5 v out cap2 cap2+ cap1 cap1+ v ss t1 t2 osc1 osc2 cl fr sync clo dyo d7 d6 d5 d4 d3 d2 d1 d0 v ss rd wr a0 c86 cs2 cs1 p/s si scl res m/s v dd v1 v2 v3 v4 v5 o0 o165 comi this drawing is not for specifying the tab outline shape.
78 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 6.3 6.3 tcp dimensions (2-sided) 6.3 tcp dimensions (2-sided) sed156xt0b figure 6.3 tcp dimensions (2-sided) 0.28 y ( + ) 47.5 nc x 2 com1 0165 5.34 28.98 ?0.04 15.16 2.70 0.5 4.40 ?.10 sr ?.50 pi 0.80 36.00 40.00 44.00 8.8 ?.7 1.5 x ( + ) SED1560t 0b nc x 2 00 d1560 nc v5 v4 v3 v2 v1 v dd v r v5 v out cap2 cap2+ cap1 cap1+ v ss t1 t2 osc1 osc2 cl fr sync clo dyo d7 d6 d5 d4 d3 d2 d1 d0 v ss rd wr a0 c86 cs2 cs1 p/s si scl res m/s v dd v1 v2 v3 v4 v5 nc note 1: 2: resist position tolerance: ?.3 product pitch: 52.25mm max 0.15 max 0.8 max 1.0
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 79 174-3.0 6.4 tcp dimensions (4-sided) 6.4 6.4 tcp dimensions (4-sided) sed156xt0a d1560 0.60 34.9750 31.82 25.95 4 ?ro. 2 26.95 22.50 18.00 4 ?ro. 2 x ( + ) 0.30 0.30 y ( + ) d1560 d1560 max 0.15 max 0.8 max 1.0 figure 6.4 tcp dimensions (4-sided)
80 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 6.5 tcp dimensions (sed1561toc) 6.5 6.5 tcp dimensions (d1561toc) 0.11 0.02 0.40 0.80 36.00 40.00 (w 0.4, g 0.4) po. 80 x 51 ?1 = 41.00 (sr) 48.34 y (+) (sr) 47.60 0.06 (w 0.14, g 0.14) po. 28 x 171 ?1 = 0.14 0.02 0.14 nc v5 v4 v3 v2 v1 vdd m/s res scl si p/s cs1 cs2 c86 a0 wr rd vss d0 d1 d2 d3 d4 d5 d6 d7 dyo clo sync fr cl osc2 osc1 t2 t1 vss cap1+ cap1 cap2+ cap2 vout v5 vr vdd v1 v2 v3 v4 v5 nc max 1.50 max 1.50 ?1.7 x (+) ?2.0 1.5 max 1.50 max 1.50 ic : sed1561dob max 1.0 max 0.8 0.28 1.98 0.01 4.75 0.01 0.14 10.23 2.54 (sr) 2.39 (sr) (sr) 8.50 28.98 0.01 (sr) 6.66 (sr) 5.34 4.40 5.28 (ic) max 8.28 8.08 (ic) max 11.08 ?2.10 sr ?1.50 pi ncx2 00 ncx2 00 ncx2 com1 0165 0.07 figure 6.5 tcp dimensions (d1561toc)
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 81 174-3.0 6.6 pad profile 6.6 6.6 pad profile tbd
82 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 symbol dimension in millimeters dimension in inches* min. nom. max. min. nom. max. ?b 0.6 0.75 0.90 (0.024) (0.030) (0.035) a 2.13 (0.084) a 1 0.5 0.6 0.7 (0.020) (0.024) (0.027) a 2 1.43 1.53 1.63 (0.057) (0.060) (0.064) q 2 25 (25 ) c 1 1.5 (0.059) c 2 1.2 (0.047) e 1.5 (0.059) d 1 23.9 24 24.1 (0.941) (0.945) (0.948) e 1 23.9 24 24.1 (0.941) (0.945) (0.948) d 27 (1.063) e 27 (1.063) * for reference table 6.2 bga 225pin package dimensions 6.7 bga package dimensions figure 6.7 plastic bga 225pin 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 qpnmlk jhgfedcba d1 d e1 e 4? 2 index 4? 1 a a 1 ? e a 2 2 SED1560b oa 6.7 6.7 bga package dimensions
s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 83 174-3.0 SED1560 SED1560 bga225 SED1560 SED1560 bga225 SED1560 SED1560 bga225 SED1560 SED1560 bga225 n/c pad# pin name pin# pad# pin name pin# pad# pin name pin# pad# pin name pin# 1v 5 b-2 55 05 r-2 109 059 k-10 163 0113 d-12 j-7 2v 4 d-4 56 06 p-3 110 060 m-13 164 0114 b-14 h-7 3v 3 b-1 57 07 k-6 111 061 n-15 165 0115 a-15 g-7 4v 2 c-2 58 08 n-4 112 062 m-14 166 0116 c-13 j-8 5v 1 f-6 59 09 r-3 113 063 j-10 167 0117 a-14 h-8 6v dd d-3 60 010 p-4 114 064 l-12 168 0118 b-13 g-8 7 m/s c-1 61 011 k-7 115 065 m-15 169 0119 e-11 j-9 8 /res d-2 62 012 m-5 116 066 l-13 170 0120 c-12 h-9 9 scl g-6 63 013 r-4 117 067 l-14 171 0121 a-13 g-9 10 si e-4 64 014 n-5 118 068 k-11 172 0122 b-12 11 p/s d-1 65 015 p-5 119 069 l-15 173 0123 f-9 12 /cs1 e-3 66 016 l-6 120 070 k-12 174 0124 d-11 13 cs2 e-2 67 017 r-5 121 071 k-13 175 0125 a-12 14 c86 f-5 68 018 m-6 122 072 k-14 176 0126 c-11 15 a0 e-1 69 019 n-6 123 073 k-15 177 0127 b-11 16 /wr f-4 70 020 p-6 124 074 j-12 178 0128 e-10 17 /rd f-3 71 021 r-6 125 075 j-13 179 0129 a-11 18 v ss f-2 72 022 m-7 126 076 j-14 180 0130 d-10 19 d0 f-1 73 023 n-7 127 077 j-15 181 0131 c-10 20 d1 g-4 74 024 p-7 128 078 j-11 182 0132 b-10 21 d2 g-3 75 025 r-7 129 079 l-8 183 0133 a-10 22 d3 g-2 76 026 l-7 130 080 k-8 184 0134 d-9 23 d4 g-1 77 027 m-8 131 081 h-10 185 0135 c-9 24 d5 g-5 78 028 p-8 132 082 h-11 186 0136 b-9 25 d6 h-3 79 029 r-8 133 083 h-6 187 0137 a-9 26 d7 h-1 80 030 n-8 134 084 h-5 188 0138 e-9 27 dyo h-2 81 031 l-9 135 085 f-8 189 0139 d-8 28 clo h-4 82 032 r-9 136 086 e-8 190 0140 b-8 29 sync j-5 83 033 p-9 137 087 h-12 191 0141 a-8 30 fr j-1 84 034 n-9 138 088 h-14 192 0142 c-8 31 cl j-2 85 035 m-9 139 089 h-15 193 0143 e-7 32 osc2 j-3 86 036 r-10 140 090 h-13 194 0144 a-7 33 osc1 j-4 87 037 p-10 141 091 g-11 195 0145 b-7 34 t2 k-1 88 038 n-10 142 092 g-15 196 0146 c-7 35 t1 k-2 89 039 m-10 143 093 g-14 197 0147 d-7 36 v ss k-3 90 040 r-11 144 094 g-13 198 0148 a-6 37 cap1 + k-4 91 041 l-10 145 095 g-12 199 0149 b-6 38 cap1 - l-1 92 042 p-11 146 096 f-15 200 0150 c-6 39 cap2 + k-5 93 043 n-11 147 097 f-14 201 0151 d-6 40 cap2 - l-2 94 044 r-12 148 098 f-13 202 0152 a-5 41 v out l-3 95 045 m-11 149 099 f-12 203 0153 e-6 42 v 5 m-1 96 046 k-9 150 0100 e-15 204 0154 b-5 43 v r l-4 97 047 p-12 151 0101 f-11 205 0155 c-5 44 v dd j-6 98 048 r-13 152 0102 e-14 206 0156 a-4 45 v 1 m-2 99 049 n-12 153 0103 e-13 207 0157 d-5 46 v 2 n-1 100 050 l-11 154 0104 d-15 208 0158 f-7 47 v 3 m-3 101 051 p-13 155 0105 e-12 209 0159 b-4 48 v 4 l-5 102 052 r-14 156 0106 g-10 210 0160 a-3 49 v 5 n-2 103 053 n-13 157 0107 d-14 211 0161 c-4 50 00 p-1 104 054 r-15 158 0108 c-15 212 0162 e-5 51 01 n-3 105 055 p-14 159 0109 d-13 213 0163 b-3 52 02 r-1 106 056 m-12 160 0110 f-10 214 0164 a-2 53 03 p-2 107 057 p-15 161 0111 c-14 215 0165 c-3 54 04 m-4 108 058 n-14 162 0112 b-15 216 comi a-1 6.8 bga pin assignment 6.8 bga pin assignment 6.8
84 174-3.0 s-mos systems, inc. ? 150 river oaks parkway ? san jose, ca 95134 ? tel: (408) 922-0200 ? fax: (408) 922-0238 s-mos assumes no responsibility or liability for (1) any errors or inaccuracies contained in the information herein and (2) the use of the information or a portion thereof in any application, including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or consequential damages. there are no warranties extended or granted by this document. the information herein is subject to change without notice from s-mos. october 1996 ? copyright 1996 s-mos systems, inc. printed in u.s.a. 174-3.0 6.9 SED1560tqa ol dimensions cu 110 +/?15um [90(+10,?0um)] 190um 0.5 +/?.1um 100% sn 25 +/?um 300um cu adhesive polymide film figure 6.8 SED1560tqa ol dimensions 6.9 6.9 SED1560tqa ol dimensions

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